High-K/ Metal Gate

In current situation of CMOS channel scaling down from 90nm to 22nm, semiconductor industries need to implement new technology to avoid high leakage on the transistor gate.

We are talking about the gate capacitance of transistor here. Gate capacitance is equal to permisivity times area per distance between two layers in the capacitor. In transistor gate, area means the product of gate length and width, while distance indicates the oxide thickness. In order to maintain equal mobility, Cox (oxide capacitance) needs to be maintained. Normally, oxide thickness is reduced to increase the gate capacitance. However, it comes with a price of introducing gate leakage. This concerns with SiO2/ Poly-Si gate. In addition, SiO2 is running out of atoms for further scaling.

Due to the concern above, high-K material is needed. K is actually equal to charge-carrier effective mobility times gate oxide capacitance per unit area. Using high-K material is like resetting the entire Tox (gate oxide thickness).

The challenge initially was on getting the pair of the high-K. Some research done showed that high-K and poly-Si are not compatible due to 2 reasons.

Firstly, it is due to Fermi level pinning at the high-K and poly-Si causing higher threshold voltage. Secondly, it is due to the fact that high-K and poly-Si exhibit severely degraded channel mobility.

Then, more researches were conducted to eventually conclude that high-K needs to be paired with metal-gate. Two key points from the discovery. Firstly, high-K/metal-gate achieves PMOS/NMOS channel mobility close to SiO2. Secondly, it shows lower gate leakage than SiO2.

As I mentioned earlier, with the invention of high-K/Metal-Gate, the oxide thickness now can be scaled back to 1.45nm. Poly-Si gate was scaled down to 0.8nm.

Cheers,
Pungky