Demographic-Economy Paradox

Have you heard of the term "Demographic-Economy Paradox"? If not, you are not the only one. I just knew this not long ago. The concept is pretty eye-openner and should be the focus of many developed nations in the years to come.

Many nations set their success based on their GDP growth and per-capita income. More developing countries are catching up with consistent above 6% GDP growth. Brazil, China, India and Russia are few nations on the high-speed growth in past decade.

So what does it have to do with demographic paradox? Well, the answer is simple. The more developed a nation is, the less tendency for working professionals to think about having more children. The more developed a nation is, the more educated the people is. They will be more cautious in their spending as well. Now, with less babies, the TFR (Total Fertility Rate) drops. This can be very damaging to replace the old workers.

A nation like Singapore is a good example. The TFR is ~1.2, which is lower than target of 2.1. With old workers now start to be in their retirement age, TFR of 1.2 can be a huge problem in ensuring proper replacement of working adults.

Worse case happens in China where they implement one-baby/child policy. This confirms of maximum TFR of 1. China can be in the turning point of slowing growth in the near terms if they are not doing anything to improve this.

Based on my rough analysis, low TFR due to high growth happens only in Asia for most of the time. Asian seems very aggressive in catching up with super-power nations from West. They can even sacrifice their family for their career. Asian has been super fast in building up their economy for the past decades, but if not controlled or balanced, rather, the turning point is just right around the corner.

Economist needs to integrate the knowlege of economy growth with the demographic mapping.

Regards,
Pungky

ATE Continuity Testing

Hi all,

I would like to share on how actually continuity testing is being done in ATE. This is very basic knowledge as an ATE engineer, so let's start with the purpose.

As you can see in the Figure on the left, continuity is trying to check input or input/output pins with single or double diode stacks.

Now, we need to ask ourselves as how to only check for the diodes and not the DUT circuits.

The way to isolate the diodes from DUT circuits is by setting the Vdd to off. This way we ensure the DUT circuits is unable to supply any voltage to their transistors.

The next question is how to check the diodes without any supply voltage. Well, the way to do that is by forcing bias current from ATE to those pins in question. The bias current will create a voltage drops across the diodes. Thus, if the connection is good, we will see some voltage across.

In order to test the upper diode stack, we need to force positive bias current and measure the voltage. Conversely, the lower diode is tested by forcing negative bias current.

Nothing compicated, isn't it?

Well, the tricky stuff is how to ensure we can catch the typical continuity defects such as pin short to ground/ VDD or pin-to-pin shorts.

When you test continuity in serial mode, that is one pin at a time, you should be able to catch those defects effectively. However, the test-time will be very long. So, normally at the beginning of the product life, we tend to do this as test-time may not be of a concern. Once, the product gets mature, we need to perform the test in parallel with a penalty of not able to catch pin-to-pin short effectively.

There is a need to fine-tune the magnitude of the bias current and the settling time. The settling time may be different from one type of digital cards to the other. So, the engineer needs to be aware how fast/ slow the paranteric measurement unit of the cards are able to provide.

I guess that's all folks.

Cheers,
Pungky




High-K/ Metal Gate

In current situation of CMOS channel scaling down from 90nm to 22nm, semiconductor industries need to implement new technology to avoid high leakage on the transistor gate.

We are talking about the gate capacitance of transistor here. Gate capacitance is equal to permisivity times area per distance between two layers in the capacitor. In transistor gate, area means the product of gate length and width, while distance indicates the oxide thickness. In order to maintain equal mobility, Cox (oxide capacitance) needs to be maintained. Normally, oxide thickness is reduced to increase the gate capacitance. However, it comes with a price of introducing gate leakage. This concerns with SiO2/ Poly-Si gate. In addition, SiO2 is running out of atoms for further scaling.

Due to the concern above, high-K material is needed. K is actually equal to charge-carrier effective mobility times gate oxide capacitance per unit area. Using high-K material is like resetting the entire Tox (gate oxide thickness).

The challenge initially was on getting the pair of the high-K. Some research done showed that high-K and poly-Si are not compatible due to 2 reasons.

Firstly, it is due to Fermi level pinning at the high-K and poly-Si causing higher threshold voltage. Secondly, it is due to the fact that high-K and poly-Si exhibit severely degraded channel mobility.

Then, more researches were conducted to eventually conclude that high-K needs to be paired with metal-gate. Two key points from the discovery. Firstly, high-K/metal-gate achieves PMOS/NMOS channel mobility close to SiO2. Secondly, it shows lower gate leakage than SiO2.

As I mentioned earlier, with the invention of high-K/Metal-Gate, the oxide thickness now can be scaled back to 1.45nm. Poly-Si gate was scaled down to 0.8nm.

Cheers,
Pungky

Standby and Active Leakage Current Control

IC power dissipation consists of standby and active leakage components. The active component is dominated by the switching or dynamic power component. In addition, the standby component can be made significantly smaller than the active component by changing the body bias condition or by power gating.

Reducing supply voltage is one way to help optimizing the power consumption. However, it will lead to slower current drive of the transistor.

Reducing supply voltage means reducing the VG or the gate voltage. Thus, due to the square component the current drive is substantially lowered too. However, we can also lower down the threshold voltage of the transistor. This is because the ON-state of the transistor is achieved when:

VGS > Vth, where Vth is the threshold voltage of the transistor. 

The threshold voltage, in turn, can be controlled by body bias voltage as shown in below equation. VSB is the source-to-body substrate bias. Normally, it is a negative value, so the more negative the back bias voltage, the higher the threshold voltage will be.

That leads to harder criteria for transistor to turn-on. Another way of reducing the threshold voltage is by thinning the oxide (related to the gamma sign in the equation).

One penalty, though, in reducing the threshold voltage is the increase in sub-threshold current as shown in the figure below.

The ISUB is thus determined by an equation that looks like the IDS current equation itself, except for several exponential numbers.


Out of several possible reasons in the high IOFF. The sub-threshold current dominates as the technology node shrinks.

In addition, the sub-threshold current increases with temperature. This is the reason why testing IDDQ at high temperature can aggravate the soft-defects especially in catching non-uniform oxide thickness issue.


Cheers,
Pungky

Electron Mobility versus Temperature

Many engineers are having misconception on the relationship between temperature and electron mobility. 

Well, if you awake only during the first 15 minutes of semiconductor fundamental lecture, then you may think that high temperature results in higher electron mobility. The answer is it depends. It is just one piece of story. 

In the first place, high temperature will help electron to excite from valence to conduction band as mentioned in my earlier post. This is related to ion impurity. As the temperature gets increased further, the lattice (phonon) start to move. As more and more electrons get excited, there is a congestion of them leading to higher probability of collisions. This slows down the mobility. The higher the doping concentration, the slower the electron mobility.

 As shown in the chart on the left, the higher the doping concentration results in higher probability of collisions. This causes the electron mobility to drop.

Then, at what temperature does the higher electron mobility be at? You may for a while think that it must have been at lower temperature. But that is not true.

 As the figure on the right shows, there is an optimum temperature whereby it yields in higher electron mobility. 

The figure illustrates clearly what I have mentioned above. There are two types of phenomena affecting the electron mobility. First being the impurity scattering and second being the lattice scattering.

The optimum temperature also depends on the doping concentration. As you see on the 5 curve lines illustrating different doping concentration. At 10^19, the optimum temperature is higher than the one for 10^18 and so on. Clearly at 10^14, the curve line is not yet shown sign of going down at ~150K. 

Well hope this helps to clear your doubts. Nothing heavy, but good enough to get us to a proper foot-ground.

Cheers,
Pungky

Basic p-n junction and MOSFET transistor

Let me share very basic concepts of semiconductor as simple as possible.

Theoretically, semiconductor materials need energy to excite its electrons from valence to conduction band. You can think of valence band as the parking lots by the side of the road. Each cars needs to be activated in order to drive its way to the main road. The main road in this case is the conduction band. The activation energy can be coming from either voltage or heat. That is also the basic of p-n junction.

Now, let's talk about the transistor itself. It is actually a combination of several p-n junction. A MOSFET transistor is analogous to a tap water. It is able to block the water from flowing and able to open the flow. So, in MOSFET, the switch lies in the gate. We apply a voltage to either turn on or off the transistor. If the absolute voltage is greater than the threshold voltage, then the transistor will be on and vice versa. The higher the gate voltage, the higher the drain-source current.

There are two possible states of transistor when gate voltage is higher than threshold voltage. First, drain-source voltage is lower than the delta between gate and threshold voltage. In this case, the transistor is at linear or triode region. The transistor is acting like a resistor. Second, drain-source voltage is greater than the delta between gate and threshold voltage. In this case, the transistor is at saturation or active mode.

That's the basic on how the p-n junction and MOSFET transistor work. Next post we will go a little bit deeper.