Hi all,
I would like to share on how actually continuity testing is being done in ATE. This is very basic knowledge as an ATE engineer, so let's start with the purpose.
As you can see in the Figure on the left, continuity is trying to check input or input/output pins with single or double diode stacks.
Now, we need to ask ourselves as how to only check for the diodes and not the DUT circuits.
The way to isolate the diodes from DUT circuits is by setting the Vdd to off. This way we ensure the DUT circuits is unable to supply any voltage to their transistors.
The next question is how to check the diodes without any supply voltage. Well, the way to do that is by forcing bias current from ATE to those pins in question. The bias current will create a voltage drops across the diodes. Thus, if the connection is good, we will see some voltage across.
In order to test the upper diode stack, we need to force positive bias current and measure the voltage. Conversely, the lower diode is tested by forcing negative bias current.
Nothing compicated, isn't it?
Well, the tricky stuff is how to ensure we can catch the typical continuity defects such as pin short to ground/ VDD or pin-to-pin shorts.
When you test continuity in serial mode, that is one pin at a time, you should be able to catch those defects effectively. However, the test-time will be very long. So, normally at the beginning of the product life, we tend to do this as test-time may not be of a concern. Once, the product gets mature, we need to perform the test in parallel with a penalty of not able to catch pin-to-pin short effectively.
There is a need to fine-tune the magnitude of the bias current and the settling time. The settling time may be different from one type of digital cards to the other. So, the engineer needs to be aware how fast/ slow the paranteric measurement unit of the cards are able to provide.
I guess that's all folks.
Cheers,
Pungky
I would like to share on how actually continuity testing is being done in ATE. This is very basic knowledge as an ATE engineer, so let's start with the purpose.
As you can see in the Figure on the left, continuity is trying to check input or input/output pins with single or double diode stacks.
Now, we need to ask ourselves as how to only check for the diodes and not the DUT circuits.
The way to isolate the diodes from DUT circuits is by setting the Vdd to off. This way we ensure the DUT circuits is unable to supply any voltage to their transistors.
The next question is how to check the diodes without any supply voltage. Well, the way to do that is by forcing bias current from ATE to those pins in question. The bias current will create a voltage drops across the diodes. Thus, if the connection is good, we will see some voltage across.
In order to test the upper diode stack, we need to force positive bias current and measure the voltage. Conversely, the lower diode is tested by forcing negative bias current.
Nothing compicated, isn't it?
Well, the tricky stuff is how to ensure we can catch the typical continuity defects such as pin short to ground/ VDD or pin-to-pin shorts.
When you test continuity in serial mode, that is one pin at a time, you should be able to catch those defects effectively. However, the test-time will be very long. So, normally at the beginning of the product life, we tend to do this as test-time may not be of a concern. Once, the product gets mature, we need to perform the test in parallel with a penalty of not able to catch pin-to-pin short effectively.
There is a need to fine-tune the magnitude of the bias current and the settling time. The settling time may be different from one type of digital cards to the other. So, the engineer needs to be aware how fast/ slow the paranteric measurement unit of the cards are able to provide.
I guess that's all folks.
Cheers,
Pungky
